On December 9th, Intel demonstrated the key technology of using back power contacts to shrink transistors to a range of 1 nanometer or more at the IEDM 2023 (IEEE International Conference on Electronic Devices). Intel stated that it will integrate 1 trillion transistors in a single package by 2030. Intel stated that it will continue to advance research on Moore's Law, including 3D stacked CMOS transistors with back powered and direct back contacts, extension paths for back powered research breakthroughs (such as back contacts), and large-scale single-chip 3D integration of silicon transistors and gallium nitride (GaN) transistors on the same 300mm wafer (rather than packaging).